Knowledge is Wealth

https://drive.google.com/file/d/119RZB7WjMeEtmo-5s-jYotCyyyOGOypz/view?usp=sharing

usp=sharing https://drive.google.com/file/d/1oUNPcspeknaLPHt1TUvrs95NG4fB93qg/view?usp=sharing https://drive.google.com/file/d/1LPA4tOl85z00FpLEBrJqI7OfRAhL9-8h/view?usp=sharing

https://drive.google.com/open?id=1fLCNrrcjBzjSrMQL8-tH6IIILWX6bpG1

https://drive.google.com/file/d/1KKT31sY5PP-OPSJoMAS1bYLS2tB05CZB/view?usp=sharing Xilinx 4000 https://www.seas.upenn.edu/~ese170/handouts/FPGA.pdf Basic IDea about FPGA https://drive.google.com/file/d/1BK2sydLF_Vt7Fj72TDm5rkH8ppmgx7Sp/view?usp=sharing

https://drive.google.com/file/d/119yx9cnb1SvxBxhNsQEHbb_3_I3w_45r/view?usp=sharing * To understand more about state Reduction watch this video https://www.youtube.com/watch?v=2JDLqfYmhDk Credits: Shibaji Paul

https://drive.google.com/file/d/1vLxS0zObABaMHrEr3UAPTTiFyR2-xeBp/view?usp=sharing Behavioural model more understanding(preferred ) 1. Case statement https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/case_statement 2. IF Statement https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/if_statement 3. for loop https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/for_loops 4. wait statement https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/wait_statement 5. Multiple Conditional Statement https://surf-vhdl.com/vhdl-case-statement/